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HMU17/883
October 1997
16 x 16-Bit CMOS Parallel Multiplier
Description
The HMU17/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier ideal for fast, real time digital signal processing applications. The 16-bit X and Y operands may be independently specified as either two's complement or unsigned magnitude format, thereby allowing mixed mode multiplication operations. Additional inputs are provided to accommodate format adjustment and rounding of the 32-bit product. The Format Adjust control allows the user the option of selecting a 31-bit product with the sign bit replicated LSP. The Round control is provided to accommodate rounding of the most significant portion of the result. This is accomplished by adding one to the most significant bit of the LSP. Two 16-bit output registers (MSP and LSP) are provided to hold the most and least significant portions of the result, respectively. These registers may be made transparent for asynchronous operation through the use of the Feedthrough Control (FT). The two halves of the product may be routed to a single 16-bit threestate output port via the output multiplexer control, and in addition, the LSP is connected to the Y-input port through a separate three-state buffer. The HMU17/883 utilizes a single clock signal (CLK) along with three register enables (ENX, ENY, and ENP) to latch the input operands and the output product registers. The ENX and ENY inputs enable the X and Y input registers, while ENP enables both the LSP and MSP output registers. This configuration facilitates the use of the HMU17/883 for micro-programmed systems. All outputs of the HMU17/883 also offer three-state control for multiplexing onto multiuse system busses.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product * High-Speed (45ns) Clocked Multiply Time * Low Power CMOS Operation - ICCSB = 500A Maximum - ICCOP = 7.0mA Maximum at 1MHz * HMU17/883 is Compatible with the AM29517, LMU17, IDT7217, and the CY7C517 * Supports Two's Complement, Unsigned Magnitude and Mixed Mode Multiplication * TTL Compatible Inputs/Outputs - Three-State Output
Ordering Information
PART NUMBER HMU17GM-45/883 HMU17GM-60/883 TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 68 Ld PGA 68 Ld PGA PKG. NO.
Functional Block Diagram
X0-15 TCX RND TCY Y0-15/P0-15
REGISTER
REGISTER
REGISTER
CLK ENX ENY MULTIPLIER ARRAY
OEL
FA FT
FORMAT ADJUST MSP REGISTER LSP REGISTER
ENP MSPSEL OEP P16-31/P0-15 MULTIPLEXER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2805.2
3-36
HMU17/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Input or Output Voltage Applied . . . . . . . . . GND 0.5V to VCC +0.5V ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Package Power Dissipation at 125 PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.17 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Die Characteristics
Number of Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4,500
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output or I/O Leakage Current Standby Power Supply Current Operating Power Supply Current SYMBOL VIH VIL VOH VOL II IO ICCSB TEST CONDITIONS VCC = 5.5V VCC = 4.5V IOH = 400A VCC = 4.5V (Note 2) IOL = +4.0mA VCC = 4.5V (Note 2) VIN = VCC or GND VCC = 5.5V VOUT = VCC or GND VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 1.0 MHz, VIN = VCC or GND VCC = 5.5V (Note 3) (Note 4) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 2.6 -10 -10 MAX 0.8 0.4 +10 +10 500 UNITS V V V V A A A
ICCOP
1, 2, 3
-55 TA 125
-
7.0
mA
Functional Test NOTES:
FT
7, 8
-55 TA 125
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 5mA/MHz. 4. Tested as follows: f = 1MHz, VIH (Clock Inputs) = 3.0, VIH (All other inputs) = 2.6, VIL = 0.4, VOH 1.5V, and VOL 1.5V.
3-37
HMU17/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUP S 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 (Note 6) 9, 10, 11 9, 10, 11 -45 -60
PARAMETER Unclocked Multiply Time Clocked Multiply Time X, Y, RND Setup Time Clock HIGH Pulse Width Clock LOW Pulse Width MSPSEL to Product Out Output Clock to P Output Clock to Y Three-State Enable Time Clock Enable Setup
SYMBOL t MUC tMC tS tPWH tPWL tPDSEL tPDP tPDY tENA tSE
(NOTE 1) CONDITIONS
TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
MIN 18 15 15 15
MAX 70 45 25 25 25 25 -
MIN 20 20 20 15
MAX 90 60 30 30 30 30 -
UNITS ns ns ns ns ns ns ns ns ns ns
NOTES: 5. AC Testing as follows: VCC = 4.5V and 5.5V. Input levels 0V and 3.0V; Timing reference levels = 1.5V; output load per test load circuit, with V1 = 2.4V, R1 = 500 and CL = 40pF. 6. Transition is measured at 200mV from steady state voltage, output loading per test load circuit, with V1 = 1.5V, R1 = 500 and CL = 40pF. TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS -45 PARAMETER Input Capacitance Output Capacitance I/O Capacitance X, Y, RND Hold Time Three-State Disable Time Clock Enable Hold Time Output Rise Time Output Fall Time NOTES: 7. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 8. Guaranteed, but not 100% tested. 9. Transition is measured at 200mV from steady state voltage; output loading per test load circuit; with V1 = 1.5V, R1 = 500 and CL = 40pF. 10. Loading is as specified in the test load circuit, with V1 = 2.4V, R1 = 500 and CL = 40pF. SYMBOL CIN COUT CI/O tH tDIS tHE tR tF From 0.8V to 2.0V From 2.0V to 0.8V CONDITIONS VCC = Open, f = 1MHz All Measurements are referenced to device GND. NOTES 7 7 7 7, 8 7, 8, 9 7, 8, 9 7, 8, 10 7, 8, 10 TEMPERATURE (oC) TA = 25 TA = 25 TA = 25 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 3 3 MAX 15 10 10 25 10 10 MIN 3 3 -60 MAX 15 10 10 30 10 10 UNITS pF pF pF ns ns ns ns ns
3-38
HMU17/883
TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
3-39
HMU17/883 Burn-In Circuit
11 N/C X13 X15 RND TCY VCC GND MSP SEL FT OEP
10
X11
X12
X14
(ENX)
TCX
VCC
GND
FA
(ENP) P30/ P14 P28/ P12 P26/ P10
N/C P31/ P15 P29/ P13 P27/ P11 P25/ P9 P23/ P7 P21/ P5 P19/ P3 P17/ P1
9
X9
X10
8
X7
X8
7
X5
X6
6
X3
X4
68 LEAD PIN GRID ARRAY
TOP VIEW
P24/ P8 P22/ P6 P20/ P4 P18/ P2
5
X1
X2
4
OEL
X0
3
(ENY)
CLK Y10/ P10 Y11/ P11 G Y12/ P12 Y13/ P13 H Y14/ P14 Y15/ P15 J
2
N/C
Y0/P0
Y2/P2 Y4/P4
Y6/P6 Y8/P8
P16/ P0 N/C K
1 A
Y1/P1 B
Y3/P3 Y5/P5 C D
Y7/P7 Y9/P9 E F
L
PGA PIN B6 A6 B5 A5 B4 A4 B3 A3 B2 B1 C2 C1 D2 D1 E2 E1 F2 NOTES:
PIN NAME X4 X3 X2 X1 X0 OEL CLK ENY Y0/P0 Y1/P1 Y2/P2 Y3/P3 Y4/P4 Y5/P5 Y6/P6 Y7/P7 Y8/P8
BURN-IN SIGNAL F6 F5 F4 F3 F2 VCC F0 F0 F2 F3 F4 F5 F6 F7 F8 F9 F10
PGA PIN F1 G2 G1 H2 H1 J2 J1 K2 L2 K3 L3 K4 L4 K5 L5 K6 L6
PIN NAME Y9/P9 Y10/P10 Y11/P11 Y12/P12 Y13/P13 Y14/P14 Y15/P15 P0/P16 P1/P17 P2/P18 P3/P19 P4/P20 P5/P21 P6/P22 P7/P23 P8/P24 P9/P25
BURN-IN SIGNAL F11 F12 F13 F14 F15 F4 F5 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
PGA PIN K7 L7 K8 L8 K9 L9 K10 K11 J10 J11 H10 H11 G10 G11 F10 F11 E10
PIN NAME P10/P26 P11/P27 P12/P28 P13/P29 P14/P30 P15/P31 ENP OEP FA FT MSPSEL GND GND VCC VCC TCY TCX
BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 F0 F1 F14 F15 F14 GND GND VCC VCC F15 F15
PGA PIN E11 D10 D11 C10 C11 B10 A10 B9 A9 B8 A8 B7 A7 A2 K1 L10 B11
PIN NAME RND ENX X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 N.C. N.C. N.C. N.C.
BURN-IN SIGNAL F1 F0 F3 F2 F15 F14 F13 F12 F11 F10 F9 F8 F7 NONE NONE NONE NONE
11. VCC = 5.0V +0.5V/-0.0V with 0.1F decoupling capacitor to GND. 12. F0 = 100kHz, F1 = F0/2, F2 = F1/2, . . . . . . . . . 13. VIH = VCC 1V 0.5V (Min), VIL = 0.8V (Max). 14. 47k load resistors used on all pins except VCC and GND (Pin Grid identifiers F10, G10, G11 and H11).
3-40
HMU17/883 Die Characteristics
DIE DIMENSIONS: 179 mils x 169 mils x 19 1 mil METALLIZATION: Type: Si-Al or Si-Al-Cu Thickness: 8kA WORST CASE CURRENT DENSITY: 1.2 x 105 A/cm2 GLASSIVATION: Type: Nitrox Thickness: 10kA
Metallization Mask Layout
HMU17/883
(8) CLKY (ENY) (7) CLKL (CLK)
(59) X10
(58) X11
(6) OEL
(57) X12
(64) X5
(63) X6
(62) X7
(61) X8
(60) X9
(5) XO
(4) X1
(2) X3
(1) X4
(3) X
(56) x 13 (55) x 14 (9) YO, P0 (10) Y1, P1 (11) Y2, P2 (12) Y3, P3 (13) Y4, P4 (14) Y5, P5 (15) Y6, P6 (16) Y7, P7 (17) Y8, P8 (18) Y9, P9 (19) Y10, P10 (20) Y11, P11 (21) Y12, P12 (22) Y13, P13 (23) Y14, P14 (24) Y15, P15 (46) GND (45) MSPSEL (44) FT (43) FA (42) DEP (41) CLKM (END) (48) VCC (47) GND (54) x 15 (53) CLKX (ENX) (52) RND (51) TCX (50) TCY (49) VCC
(35) P10, P26
(36) P11, P27
(37) P12, P28
(38) P13, P29
(39) P14, P30
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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3-41
(40) P15, P31
(25) P0, P16
(26) P1, P17
(28) P3, P19
(29) P4, P20
(30) P5, P21
(31) P6, P22
(32) P7, P23
(33) P8, P24
(34) P9, P25
(27) P2, P18

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